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Paper IPM / Computer Science / 11121

School of Computer Science

Title:

Fault detection enhancement in cache memories using a high-performance placement algorithm

Author(s):

1 .	H. R. Zarandi
2 .	S.G. Miremadi
3 .	H. Sarbazi-Azad

Status:

In Proceedings

Proceeding:

Year:

2004

Pages:

101

Publisher(s):

IEEE Computer Society

Supported by:

IPM

Abstract:

Data integrity of words coming out of the caches needsto be checked to assure their correctness. This paperproposes a cache placement scheme, which provides highperformance as well as high fault detection coverage. Inthis scheme, the cache space is divided into sets ofdifferent sizes. Here, the length of tag fields associated toeach set is unique and is different from the other sets. Theother remained bits of tags are used for protecting the tagusing a fault detection scheme e.g., generalized parity.This leads to protect the cache without compromisingperformance and area with respect to the similar one,fully associative cache. The results obtained fromsimulating some standard trace files reveal that theproposed scheme exhibits a performance near to fullyassociative but achieves a considerable fault detectioncoverage which is suitable to be used in the dependable computing.

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